加拿大专利CA2255107A1 Programmable input/output circuit for fpga for use in ttl, gtl, gtlp, lvpecl and lvds circuits

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专利摘要:
A programmable input/output structure comprised of three input circuits and one output circuit coupled to the pin of an FPGA with the input circuits and output circuits being selectively enabled by programming bits so that input signals may be accepted from TTL, GTL, GTLP, LVPECL or LVDS type external circuits. The programming bits can also selectively enable an output driver to simultaneously drive the same pin of the FPGA as an output with signals which are either TTL or GTL or GTLP compatible. Further, the slew rate of the output driver is programmable between slow, medium or fast.
公开号:CA2255107A1
申请号:C2255107
申请日:1998-12-04
公开日:2000-05-25
发明作者:Suresh Manohar Menon；Yogendra Kumar Bobra；Atul V. Ghia；Arch Zaliznyak
申请人:Suresh Manohar Menon；Yogendra Kumar Bobra；Atul V. Ghia；Arch Zaliznyak；
IPC主号:H03K19-01

专利说明:
[1" class="description-paragraph]
[2" class="description-paragraph] 2 The invention is useful in the field of FPGA designs, and, more
[3" class="description-paragraph] 3 particularly, in FPGAs that are to be used in circuits where input signals may
[4" class="description-paragraph] 4 be received from TTL, GTL, GTLP, LVPECL or LVDS circuits or which may have to drive TTL, GTL or GTLP circuits.6 FPGAs frequently are used to implement certain functions in other 7 circuits and to provide flexible functionality. However, the number of potential 8 applications for FPGAs is huge so FPGAs will be called upon in various 9 applications to receive input signals from a large variety of different types of circuits having different voltage swing standards between logic 1 and logic 0.11 Likewise, FPGAs will be called upon in various applications to drive a variety 12 of different types of circuits with output signals which must meet the standards 13 of voltage level for logic 1 and logic 0 of the driven circuit.14 Prior art FPGAs have difficulty adapting to use in different applications with circuits driving their input pins with voltage levels which are different than 16 the voltage levels for which the circuitry inside the FPGA was designed for.17 Likewise, prior art FPGAs have difficulty driving circuitry that require input 18 signals with logic levels which have different voltages than the voltage levels 19 the FPGA is designed to generate. Prior to this invention, only one I/Ostandard had been offered for FPGAs. That standard was a CMOS I/O which 21 was TTL compatible with slew rate control. This means that the output is 22 CMOS but the logic swings are TTL compatible with some programmability of 23 slew rate control. However, there are other logic families for CMOS and TTL, 24 and new families are being developed. Other families include GTL, GTLP, LVPECL and LVDS. Each of these other families has different requirements 1 for logic 0 and logic 1 voltage levels, voltage reference levels, offset and/or 2 swing. Prior art FPGA CMOS I/0 circuits either have difficulty being 3 compatible with these diverse standards or require external conversion 4 circuitry to be compatible. Thus a need has arisen for an FPGA with a programmable I/0 circuit 6 which can accept input signals from many different types of logic families and 7 complying with their native standards and which can drive circuits from 8 different logic families in accordance with their diverse standards. SUMMARY OF THE INVENTION11 The genus of the invention includes any programmable circuitry that 12 can be configured with programming bits to assume any one of the 13 configurations given in Figures 1 through 6 or any other FPGA driver or input 14 circuits already existing or developed in the future to drive signals to external circuits off the FPGA or receive signals into the FPGA from off-chip circuits in 16 new technology families already developed, in the process of development or 17 to be developed in the future. Essentially, the invention is a programmable 18 I/O circuit for an FPGA which, by changing some programming bits, can be 19 transformed into any one of the FPGA driver or input circuits shown in Figures 1-6 or any other currently existing input circuit or driver for an FPGA which 21 currently exists but is not supported by the products of the assignee or which 22 is developed in the future. Essentially, the details of the actual input circuits 23 themselves or drivers themselves on board the FPGA are not important since 24 these circuits are already known or will become known in the future. It is the progammability to transform a programmable input circuit or driver from an 1 input circuit or driver compatible with a first technology family to an input 2 circuit which is compatible with a second technology family or any other logic 3 family that is the essence of what is new. The exact details of how the 4 programmability is achieved are not critical, so long as the FPGA I/0 circuit is programmable so as to be compatible with existing or future developed off 6 chip technology families.7 A subgenus within this main genus includes programmable slew rate.8 This is achieved by having multiple parallel transistors either with different 9 channel widths which may be substituted or by having multiple parallel transistors all with the same channel width which may be added in parallel to 11 add additional current sinking or current sourcing capability to alter the slew 12 rate. 14 Figure 1 is a circuit diagram of an FPGA driver known in the prior art that can drive TTL circuits;16 Figure 2 is a circuit diagram of an FPGA driver that can drive GTL or 17 GTLP circuits;18 Figure 3 is a circuit diagram of an FPGA input circuit that can accept 19 input signals from TTL circuits; Figure 4 is a circuit diagram of an FPGA input circuit which can receive 21 signals from GTL or GTLP family circuits;22 Figure 5 is a circuit diagram of an FPGA input circuit which can receive 23 signals from LVPECL and LVDS circuits; and 24 Figure 6 is a circuit diagram of an FPGA driver circuit which can drive AGTL, HSTL or SSTL circuits. 3 CMOS FPGAs that need to be used with other circuit families must be 4 able to receive input signals at the voltage levels generated by those circuits or generate output signals that those other circuit families are compatible with.6 For example, the TTL family standards are: logic 0 = 0.4 volts (hereafter V), 7 logic 1 = 2.4 V and the reference voltage is 1.3 V-1.SV. The GTL logic family 8 standard is an open drain family: logic 0 = 0.4 V, logic 1 = 1.2 V and the 9 reference voltage is 2/3 VTT where VTT is 1.2 V and a load resistance of 50 ohms is required. The GTLP logic family standard is: logic 0 = 0.55 V, logic 1 11 = 1.5 V and the reference voltage is 2/3 VTT where VTT is 1.5 V and a load 12 resistance of 25 ohms is required. The LVPECL (Vcc = 3.3 volt positive 13 supply, emitter coupled logic) single ended and differential logic family 14 standard is: logic 0 = Vcc - 1.7 V, logic 1 = Vcc - 0.8 V and the reference voltage is Vcc - 1.3 V. The LVDS or low voltage differential signalling family is 16 a CMOS technology requiring an offset of 1.2 V and a logic swing of 345 17 millivolts between the logic 0 and logic 1 levels.18 The GTL (Gunning transistor logic which is like ECL in CMOS) and 19 GTLP or GTL Plus standards were developed in an effort to get more speed out of CMOS circuitry. Still newer logic families such as AGTL, HSTL 1, 2, 3 21 or 4 and SSTL are also either currently in existence or being developed in an 22 attempt to get still more speed out of CMOS. The AGTL family is being 23 developed by Intel and stands for assisted GTL. This technology is 24 essentially a combination of the circuits of Figure 1 and 2 to add a P-channel device to the circuit of Figure 2 to assist pullup of the voltage on node 42 to
[5" class="description-paragraph] 5 1 make it faster. Newer technologies will continue to be developed, so the 2 inportance of programmable I/0 circuits that can drive different technology 3 families or receive input signals therefrom will become ever more important.4 The I/O circuitry disclosed herein for an FPGA according to the invention is programmable to receive input signals from or drive output signals
[6" class="description-paragraph] 6 to any of the TTL, GTL or GTLP families and can receive input signals from
[7" class="description-paragraph] 7 the LVPECL or LVDS families. Other circuitry suitable to programmably drive
[8" class="description-paragraph] 8 TTL, GTL, GTLP, LVPECL or LVDS circuits will be apparent to those skilled in
[9" class="description-paragraph] 9 the art given their knowledge of the art and the guidance given herein as to specific circuits to drive TTL, GTL or GTLP circuits or receive inputs from TTL, 11 GTL or GTLP as well as LVPECL or LVDS circuits. The I/O circuitry inside 12 the FPGA coupled to each pin can be programmed individually such that the 13 FPGA can receive input signals at a particular pin from any of the TTL, GTL, 14 GTLP, LVPECL or LVDS families and drive output signals to any of the TTL, GTL or GTLP families such that the FPGA can act as a level translator and 16 conversion circuit between diverse logic families. Each FPGA output has 17 programmable slew rate control and has 3-state capability. When set to TTL18 mode, the FPGA IIO circuits according to the invention are 100% compatible 19 with 33 MHz and 66 MHz PCI busses. In the preferred embodiment, four separate and different 21 programmable I/0 circuits are used to support the five logic families: TTL, 22 GTL, GTLP, LVPECL and LVDS. The first programmable input circuit 23 receives input from TTL family off chip circuits. The second programmable 24 input circuit receives input from GTL and GTLP off chip circuits. The third programmable input circuit receives input only from the LVPECL and LVDS 1 logic families. A fourth programmable output circuit generates output signals 2 for either TTL or GTL or GTLP off chip circuits at the same pin or pad that 3 input data is received on. Most of the FPGA pins have both programmable 4 input circuits and programmable output circuits present and connected to the same pin so that input signals can be received from all five logic families or 6 output signals can be generated which are compatible with the TTL, GTL or 7 GTLP families. Others of the pins have only the first type programmable I/0 8 circuit or the second type programmable I/0 circuit present so not all logic 9 families can be supported at all pins. In other embodiments, all I/O pins will have both types of programmable I/0 circuits so that any pin can support all 11 five logic families.12 To best understand the characteristics that the programmable I/O13 circuits must have to be compatible with a plurality of logic families, it is best 14 to start with the individual driver circuits and individual input circuits for each logic family which would have to be present inside an FPGA to be able to 16 drive output signals to a particular logic family with compatible voltage levels 17 or receive input signals from a circuit in a particular logic family and convert 18 them to the voltage levels used inside the FPGA for logic 1 and logic 0. The 19 internal logic of the FPGA will be assumed to be CMOS. Specific programmable circuits will be taught herein which can programmably perform 21 the functions of any one of the drivers or input circuits disclosed below in 22 Figures 1-6, but those skilled in the art will appreciate other circuits which also 23 may be used to programmably Omasquerade0 or perform the equivalent 24 functions of any of the drivers and input circuits disclosed in Figure 1-6 given 1 the example detailed herein without departing from the spirit and scope of the 2 invention.3 Figure 1 is a diagram of a typical prior art CMOS TTL driver that has 4 been used in FPGAs in the prior art to generate TTL level output signals at output pin 20. The driver is comprised of a pair of CMOS transistors including 6 a P channel device 22 and an N channel device 24 coupled in series between 7 high and low rails 26 and 28. The channel sizes of the transistors 22 and 24 8 are selected to establish the required current drive capacity to meet the 9 required slew rate. To generate a logic 1, the FPGA logic block 31 generates a logic 0 on each of lines 30 and 32. To generate a logic 0, the logic block 11 generates a logic 1 on both of lines 30 and 32. To tristate the output, the logic 12 block generates true and complement signals on lines 30 and 32 such that 13 both CMOS transistors 22 and 24 are turned off. These logic signals control 14 the conductivity states of transistors 22 and 24 such that either transistor 22 is on and transistor 24 is off thereby coupling line 20 to the high rail 26, or 16 transistor 24 is on and transistor 22 is off thereby connecting line 20 to low rail 17 28. The voltages on the high and low rails are such that the logic swing on 18 output pin 20 is compliant with TTL standards. The FPGA logic block is 19 usually connected to lines 30 and 32 through programmable Oactive links such as are defined in co-pending U.S. patent application serial number 21 08/978,691, filed 11/26/97 which is hereby incorporated by reference. An 22 active link is a programmable connection circuit which selectively connects 23 line segments of the same line in a bus using an MOS or bipolar transistor 24 such that gain is supplied to reconstruct the signal such that the losses are replenished and the signal is reconstructed. The active link also serves to 1 compartmentalize the parasistic capacitances affecting the line segments 2 such that drivers connected to each line segment can be optimized for the 3 parasitic capacitances on that line segment alone and subsequent routing 4 decisions do not affect the amount of parasitic capacitance the driver must contend with. Active links are not necessary to practice the invention of 6 course and any other prior art structure for selectively connecting logic blocks 7 to pins in FPGAs such as fusible links etc. may be substituted and are 8 deemed equivalent.9 Figure 2 is a diagram of an open collector driver for an FPGA which is compatible with the GTL and GTLP logic families. This driver is comprised of 11 a single NMOS device 34 with its source coupled to the low rail 36 and an 12 open drain. The size of the channel of transistor 34 is selected to meet the 13 drive capability, i.e., current supply minimum and Vol max (logic 0 maximum 14 voltage) with a specified load resistance and provide some slew rate adjustment as specified in the GTL or GTLP family specification. The drain 44 16 is the output pin and the signal generated by the FPGA logic block 45 is 17 coupled (usually selectively coupled via an active link or other programmable 18 connection) to the gate 46 to turn transistor 34 on or off. The drain is coupled 19 to the high rail 40 through an external load transistor 38 such that the output signal can be taken off node 42. The high rail supplies a voltage VTT to the 21 device through the load resistor. As was the case for Figure 1, the values of 22 voltage on the high and low rail are established to set the logic 1 and logic 0 23 levels properly for either the GTL or GTLP standard. The value of load 24 resistor 38 is established at 50 ohms if the driver is to be used to drive a GTL 1 family circuit and 25 ohms if the driver is to be used to drive a GTLP family 2 circuit.3 Referring to Figure 3, there is shown a prior art CMOS input circuit 4 compatible with TTL levels which has been used on prior art FPGAs to receive signals from TTL circuits and couple them to an FPGA logic block.6 The circuit is comprised of a PMOS transistor 50 and an NMOS transistor 52 7 which have their gates coupled to the FPGA input pin 54. The two MOS8 transistors are coupled in series as a CMOS pair between a high rail 56 and a 9 low rail 58 which supply voltages selected to convert the TTL logic swings on line 54 to CMOS logic swings used internally in the logic blocks of the FPGA.11 The output logic signals on line 59 are selectively coupled through active links 12 or other FPGA programmable connections to an FPGA logic block 60. The 13 size of the channels of transistors 50 and 52 are selected to establish any 14 required current sink capability. Referring to Figure 4, there is shown a diagram of the type of input 16 circuit useable to receive signals from GTL or GTLP families. The input circuit 17 comprises a differentially coupled pair of PMOS devices 62 and 64 with 18 device 62 having its gate 66 being the FPGA input pin and coupled to receive 19 a single ended signal from the external GTL or GTLP circuit. The gate 68 of device 64 is coupled to receive a reference voltage for single ended input 21 signals and to receive the complementary signal to the signal on line 66 in the 22 case of differential input signals. The drains of transistors 62 and 64 are 23 coupled through a PMOS bias transistor 70 to the high rail 72. The gate 74 of 24 transistor 70 receives a bias control signal which controls the amount of current flowing through devices 62 and 64. A pair of NMOS devices 72 and 1 74 receive gate signals on lines 76 and 78 which control the conductivity of 2 the channels of devices 72 and 74 such that they act as a load. The sources 3 of devices 72 and 74 are coupled to the low rail 80. The logic 1 and logic 0 4 voltages are established at output 82 to drive FPGA logic block 84 through a programmable active link repeater 86 which also functions to selectively 6 couple output 82 to FPGA block 84 as well as provide buffering and inversion.7 In other embodiments, the active link may be omitted and some other 8 selective connection FPGA link such as a fusible link may be substituted. The 9 voltage levels generated for logic 0 and logic 1 are dependent upon the voltages on the high and low rails 72 and 80 and the resistance values of the 11 loads 72 and 74 as established by the control signals on lines 76 and 78 and 12 the amount of current flowing in the devices 62 and 64 as established by their 13 channel width and the value of the bias current generated by transistor 70.14 The logic level of the input signal on line 66 relative to the reference voltage on line 68 causes the transistors 62 and 64 to steer current either down the 16 left branch through load 72 or through the right branch through load 74 to 17 cause the voltage swings on output line 82. The foregoing description 18 assumes a single ended signal. However, by substituting the complementary 19 signal for the reference signal on line 68, the input circuit can be used to receive differential GTL or GTLP signals.21 Referring to Figure 5, there is shown an FPGA input circuit for LVPECL22 and LVDS family circuits driving the input pin of the FPGA. The circuit is 23 comprised of a differentially coupled pair of NMOS devices 88 and 90 with the 24 gate of transistor 88 coupled to the input pin of the FPGA through a programmable FPGA connection structure such as an active link repeater _~ _ _ _ __ ___ __ _._._..___ 1 which is controlled to either make the connection or block it depending upon 2 the state of PGM signal on line 94. The sources of transistors 88 and 90 are 3 coupled to a low rail voltage supply line 96 through an NMOS bias transistor 4 98. This transistor receives NBIAS signal on line 100 to control the amount of current flow through devices 88 and 90. PMOS load transistors 102 and 104 6 receive load bias control signals on line 106 and 108 to control their 7 resistivities so as to establish load resistances. The drains of the load devices 8 are coupled to the high rail 110. As was the case for the input circuit of Figure 9 4 described above, the voltage levels generated for logic 0 and logic 1 are dependent upon the voltages on the high and low rails and the resistance 11 values of the loads and the amount of current flowing in the devices 88 and 12 as established by their channel width and the value of the bias current 13 generated by transistor 98. The logic level of the input signal on line 116 14 relative to the reference voltage on line 117 causes the transistors 88 and to steer current either down the left branch through load 102 or through the 16 right branch through load 104 to cause the voltage swings on output line 118.17 The foregoing description assumes a single ended signal. However, by 18 substituting the complementary signal for the reference signal on line 117, the 19 input circuit can be used to receive differential signals. Referring to Figure 6, there is shown a circuit diagram for an FPGA21 driver capable of driving the AGTL, HSTL and SSTL families of circuits. The 22 driver consists of a CMOS pair of transistors 120 and 122 coupled between a 23 high rail voltage supply 124 and a low rail voltage supply 123. The actual 24 output pin of the FPGA is symbolized by node 126. Dashed line symbolizes 1 an off-chip connection to a load resistor 130 which couples the high rail supply 2 voltage VTT to node 126.3 The genus of the invention includes any programmable circuitry that 4 can be configured with programming bits to assume any one of the configurations given in Figures 1 through 6 or any other FPGA driver or input 6 circuits developed in the future to drive signals to external circuits off the 7 FPGA or receive signals into the FPGA from off-chip circuits in new 8 technology families to be developed in the future. Essentially, the invention is 9 a programmable I/0 circuit for an FPGA which, by changing some programming bits, can be transformed into any one of the FPGA driver or 11 input circuits shown in Figures 1-6 or which will be developed in the future.12 The exact details of how the programmability is achieved are not critical, so 13 long as the FPGA I/O circuit is programmable so as to be compatible with 14 existing or future developed off chip technology families. A subgenus within this main genus includes programmable slew rate.16 This is achieved by having multiple parallel transistors either with different 17 channel widths which may be substituted or by having multiple parallel 18 transistors all with the same channel width which may be added in parallel to 19 add additional current sinking or current sourcing capability to alter the slew rate. Typical values for programmable slew rates are given in the publicly 21 available data sheet for the DL6000 family of FPGAs offered by the assignee 22 of the present invention, which is hereby incorporated by reference. 1 Referring to Figure 7, there is shown a top level block diagram of an 2 example and the preferred embodiment of an FPGA programmable 3 input/output (hereafter I/O) circuit. This circuit includes a TTL input circuit 150 4 which implements the function of the circuit of Figure 3, a GTL and GTLPinput circuit 152 which implements the function of the circuit of Figure 4 and a 6 LVPECL and LVDS input circuit 154 which implements the function of the 7 circuit of Figure 5. The TTL input circuit 150 has an output 160 which is also 8 coupled to the outputs of the GTL and GTLP input circuit 152 and the 9 LVPECL and LVDS input circuit 154. Each of these outputs can be put in tristate isolation by programming bits so only one input circuit at a time is 11 driving output line 160. Output line 160 is coupled to a boundary scan circuit 12 166 that does not form part of the invention. The boundary scan circuit 13 couples input and output signals from pin 156 through the various input 14 circuits and drivers to the matrix of logic blocks in the FPGA array. The input signal to the FPGA from some off chip circuit in one of these 16 families arrives on pin 156 and is coupled through resistor 158 to each of 17 these input circuits 150, 152 and 154 via line 159. The circuit is 18 programmable such that only one of the input circuits 150, 152 and 154 is 19 turned on at any particular time and the others are disabled such that they do not act on the input signal and their outputs are placed in tristate isolation. In 21 alternative embodiments, the circuit of Figure 7 also includes an driver circuit 22 that implements the function of the AGTL, HSTL and SSTL input circuit of 23 Figure 6. 1 If the circuit driving the pin 156 is a TTL circuit, then a TTL*2 programming bit on line 172 is set to logic 0 and a PGM MODE STD signal on 3 line 174 is set to logic 0 so as to not block the action through the NOR gate of 4 the programming bit on line 172. This causes NOR gate 176 to drive TTLON* (* indicates signal is active low) line 170 to logic 1. This turns on input 6 circuit 150 and it then acts on the input signal on line 156 as the circuit of 7 Figure 3 acts on the signal on line 54 to convert it to the logic levels in use 8 inside the FPGA on line 59. At the same time, all the other input circuits 9 and 154 are turned off by virtue of their programming bits set to logic 1 and their outputs are tristate so as to not affect the voltage level on line 160.11 Specifically, the other input circuits 152 and 154 are disabled by setting their 12 programming bits, specifically, GTL* on line 182 and LVPECL* on line 186, to 13 logic 1 so that their power down signals on lines 184 and 190 are set to logic 14 0 to power down the other input circuits. That is, when the GTL*programming bit on line 182 is high, NOR gate 180 drives the GTL ON* signal 16 on line 184 to logic 0 which disables GTL and GTLP input circuit 152. When 17 the LVPECL programming bit is high, NOR gate 188 drives LVPECL ON*18 signal on line 190 to logic 0 which disables LVPECL and LVDS input circuit 19 154. The other input circuits can be turned on in a similar fashion by 21 manipulation of the programming bits so that only one is enabled at any 22 particular time. When the GTL and GTLP input circuit is enabled, a reference 23 voltage corresponding to the reference voltage on line 68 in Figure 4 is 24 applied to line 151. A GTL BIAS signal supplied via line 149 corresponds to 1 the bias signal on line 74 in Figure 4 and controls the level of current flow 2 through a pair of differentially coupled CMOS pairs inside block 152.3 The term C~programming bits refers to enable or steering signals the 4 logic state is set by the logic 0 or logic 1 state of a programming bit in a memory. The function and configuration of an FPGA is defined by 6 programming bits which are stored in internal memories in the FPGA when 7 the chip is set up.8 When any one of the enable or power down signals on lines 170, 184 9 or 190 is in a logic 1 state indicating an input circuit is enabled, OR gate drives line 194 to logic 1 which turns off PMOS pullup transistor 196 off so 11 that output line 160 is left to be driven to either logic 0 or logic 1 depending 12 upon the state of the input signal on line 156. When all of the input circuits 13 150, 152 and 154 are disabled, all three input signals to OR gate 192 are logic 14 0 so line 194 is logic 0. This causes pullup transistor 196 to be turned on and connects output line 160 to the high rail 197 to prevent output line 160 from 16 floating so that it can never be in an unknown state.17 The LVPECL and LVDS input circuit 154 is also programmable as to 18 whether it receives a single ended input signal or a differential input signal by 19 virtue of the operation of multiplexer 155. A single ended signal arrives on line 156 when the LVPECL and LVDS input circuit 154 is activated, and 21 multiplexer 155 is controlled by the programming bit on line 157 to select the 22 reference voltage REF on line 159 for coupling to the input line 163. Input line 23 163 corresponds to input 117 in Figure 5. If differential input signals are being 24 received from the external circuit, the programming bit on line 157 is set to select the differential signal suppled to pin 161 by the external circuit for 1 coupling to line 163. The programming bit on line 157 is the REF/DIF signal 2 on line 167 which drives line 157 through inverter 169. The bias level to the 3 LVPECL and LVDS input circuit 154 is controlled by the signal on line 165. A4 straightforward modification of the circuit of Figure 7 to add a multiplexes like multiplexes 155 to control the data inputs to the GTL and GTLP input circuit 6 152 will allow the GTL or GTLP input circuit to receive either differential or 7 single ended GTL or GTLP signals.8 The PGM MODE STD signal on line 174 is an optional enhancement 9 which allows all I/O pins to be controlled to have one known state during programming mode to configure the chip by setting the various programming 11 bits to their desired logic states. This signal comes from the configuration 12 logic and is set to a particular logic state during programming mode so that all 13 I/O pins have a known state during programming. The PGM MODE STD is a 14 global override signal which is activated during the programming mode to a logic 1 for all I/0 pins that are to be disabled. When the PGM MODE STD16 signal is set to a logic 1 during programming, it causes the output of the NOR17 gates to ignore their programming bits and hold the power down signals, on 18 lines 170, 184 and 190 at logic 0. This disables all the input circuits 150, 152 19 and 154 so they cannot act on signals at the input pins and ignore their programming bits.21 The configuration logic sets the state of the PGM MODE STD signals 22 to groups of I/O pins individually during programming mode to disable some 23 groups of pins and enable others. In other words, each I/O pin gets a PGM24 MODE STD signal from the configuration logic, but these signals do not all have to be in the same state. During programming, the TTL, GTL and 1 LVPECL programming bits are not programmed yet, but all come up in a 2 known logic 0 state. This allows some pins to be enabled in a known state 3 during programming and others to be disabled.4 Output driver circuit 200 contains the predriver and final driver for each circuit family that the FPGA can provide output signals to. In the currently 6 implemented embodiment, the circuit 200 contains only output drivers for TTL, 7 GTL and GTLP logic families. However, in other species, output circuit will 8 include output drivers for the recently introduced AGTL, HSTL, SSTL families 9 and for the LVPECL and LVDS families. Driver circuits to convert from CMOSlevels to the voltage levels, reference voltages and slew rates for the AGTL, 11 HSTL, SSTL families and for the LVPECL and LVDS families are known in the 12 prior although not in the FPGA art. These circuits may be integrated into 13 CMOS on the FPGA and included as part of circuit 20 with suitable enabling 14 circuitry such that the proper one of these driver circuits may be enabled to drive pin 156 as an output with all the other drivers turned off. The output 16 circuit 200 also has a programmable slew rate between fast, medium and 17 slow settings. The input circuits have high impedance CMOS inputs so they 18 do not have programmable sink rates for current as they do not load down the 19 circuits that drive pin 156. The particular type of output driver between TTL and GTL or GTLP and 21 the particular slew rate or current drive capability in effect are controlled by 22 three bits on bus 202 from the configuration logic (not shown). The output line 23 of the driver circuit is the line coming out the left side of block 200 and 24 connected to pin 156. The two programming bits from the configuration logic which control the slew rate are input as the two bits on the slew rate input 1 signals bus 204 through inverter 206 to set the values of the two slew rate bits 2 on bus 202. The third configuration bit on bus 202 controls whether the 3 internal GTL and GTLP driver or the TTL driver is enabled. This third 4 configuration bit is the ouput signal GTL ON* output by NOR gate 180 in response to the GTL* programming bit on line 182. If the GTL* programming 6 bit has the GTL and GTLP input circuit enabled, the GTL and GTLP output 7 circuit will also be enabled to drive output signals out pin 156. If GTL* is not 8 asserted (logic 1 ), the TTL output driver in box 200 is enabled and pin 156 will 9 be a TTL output. It is possible to disable the TTL or GTL and GTLP output circuit without disabling the selected TTL or GTL and GTLP input circuit by 11 asserting an output enable signal OEN* on line 208. When this signal is 12 asserted low, the output line 156 will be enabled and the driver will be enabled 13 and drive output line 156 in accordance with the input data on line 214. When 14 OEN* is logic 1, output line 156 is placed in tristate mode and the internal TTLand GTL or GTLP drivers will be disabled. OEN* is asserted by programming 16 bits in the FPGA logic block array or output multiplexers which are not shown.17 The output line 156 has 4 different states in the preferred embodiment 18 because some users like to control the state of their bus line connected to pin 19 156 when the output line from output driver 200 is tristate. The states of output line 156 are on and driven, tristate float, tristate pulled up and tristate 21 pulled down. The last two states are optional and implemented by 22 programmable PGUP and NGDN signals on lines 210 and 212, respectively.23 These signals are controlled by programming bits on lines 211 and 213, 24 respectively. 1 The DATA IN signal on line 214 is the data signal generated by the 2 logic blocks of the FPGA array which is fed to the input of the TTL or GTL3 driver and corresponds to line 30 in Figure 1 or line 46 in Figure 2.4 Lines 216 and 218 are the high and low rails, respectively to supply power to the driver circuit. Line 220 is a substrate tap and is the equivalent of 6 a quiet, low noise low rail voltage supply.7 Any circuitry known in the prior art which is capable of performing the 8 functions of the drivers and input circuits of Figures 1 through 6 and which is 9 capable of being modified so that it may be enabled and disabled by programming bits and which may be integrated onto an FPGA may be used to 11 implement the functions of blocks 150, 152, 154 and 200 in Figure 7.12 Examples of specific circuits are given below.13 Referring to Figure 8, there is shown an example of the preferred form 14 of TTL input circuit that implements the functions of block 150 in Figure 7.Transistor 250 is the PMOS transistor corresponding to transistor 50 in Figure 16 3, and transistor 252 is the NMOS device corresponding to transistor 52 in 17 Figure 3. The data input signal is applied to line 156 corresponding to line 54 18 in Figure 3 and line 156 in Figure 7. The high rail connection corresponding 19 to 56 is Figure 3 is at 256, and the low rail connection is at 258. Transistor 260 is the enable transistor. When transistor 260 is on, the CMOS pair 21 comprised of transistors 250 and 252 are connected to the low rail 258 and 22 operate to convert the TTL levels at input 156 to CMOS output levels on 23 output 160. A tristate buffer 262 functions to allow output signals on segment 24 264 output by final driver inverter 266 to drive output line 160 when the TTLinput circuit is enabled and to tristate line 160 when the TTL input circuit is 1 disabled. PMOS device 286 is a second enabling transistor which turns on 2 when TTL ON* is low thereby raising the source of PMOS device 250 to the 3 level of the high rail thereby disabling it since the drain of device 250 is 4 always coupled to the high rail. PMOS transistor 288 is coupled as a resistor Two pairs of CMOS devices comprised of PMOS transistor 268 and 6 NMOS transistor 270 and PMOS transistor 272 and NMOS transistor 274 are 7 provided optionally (by use of a metal mask option) to enable adjustment of 8 the trigger point using metal options. In case the devices sizes selected for 9 the CMOS pair 250 and 252 do not work out in the final silicon to provide the proper threshold voltages for proper TTL to CMOS conversion, the differently 11 sized pairs can be turned on by changing the metal mask to change the 12 thresholds. This is a pure practicality based upon the fact that simulation 13 results do not always agree exactly with actual results given the vagaries of 14 the process of manufacturing the device. The input signal on line 156 is currently coupled via metal option line segments 276, 280, 278 and 282 to 16 the gates of the CMOS pairs so that PMOS devices 250, 268 and 272 are all 17 activated and all act on the input signal on line 156. A fourth PMOS device 18 288 is turned off by metal option line segment 290 so it does not act on the 19 input signal. Likewise, three NMOS devices 252, 270 and 274 are all connected via metal option line segments so as to act on the input signal on 21 line 156. Each CMOS pair is coupled to output line segement 284. In a 22 subsequent design cycle spin, the three PMOS and three NMOS transistors 23 may be omitted and a single PMOS and single NMOS transistor of the proper 24 sizes to achieve the desired threshold may be substituted for equivalent operation. 1 Referring to Figure 9, there is shown an example of the preferred form 2 of GTLP and GTL input circuit to implement the function of block 152 in Figure 3 7 and act like the circuit of Figure 4. If the input data from the off chip GTL4 circuit is single ended, it is applied to pin 156, and a reference voltage compatible with the GTL/GTLP standard is applied to line 151. If the input 6 data from the off chip GTL or GTLP circuit is differential, the true version is 7 applied to line 156 and the complement version is applied to line 151 which 8 correspond to like numbered lines in Figure 7. PMOS transistors 300 and 302 9 correspond to transistors 62 and 64 in Figure 4 and perform the same function in the combination. NMOS transistors 304 and 306 function as the load 11 devices for transistors 300 and 302 and correspond to transistors 72 and 74, 12 respectively, in Figure 4.13 Transistor 308 is an adjustable current source which corresponds to 14 transistor 70 in Figure 4 and connects the high rail 72 to the PMOS devices 300 and 302 to drive an adjustable amount of current therethrough. The GTL16 BIAS signal on line 149 controls the current level that flows through the 17 CMOS pairs and gets steered by the input data through one branch or the 18 other. Transistor 312 is a metal option transistor that can be added to adjust 19 the bias but which is shown as currently inoperative by virtue of its gate being connected to its drain.21 When the GTL ON* signal is asserted to logic 0 to power down the 22 input circuit, inverter 316 drives line 318 to logic 1. This turns off PMOS23 transisistor 320 and turns on NMOS transistor 322 thereby shorting the gates 24 of load transistors 304 and 306 to ground or low rail 80 thereby disabling these load transistors such that they look like very high impedances to the 1 active devices 300 and 302 which receive the input data. The active devices 2 are thus disabled and do not translate the input data at GTL levels to the 3 CMOS logic levels on output line 324. When GTL ON* is logic 1, the GTL and 4 GTLP input circuit is rendered operational by turning on transistor 320 and turning off transistor 322. This shorts the gates of load transistors 304 and 6 306 to their drains and the sources of the active devices 300 and 302. This 7 causes load devices 304 and 306 to be variable resistors depending upon the 8 state of the input data thereby enabling the logic level conversion process.9 When GTL ON* is active low and the circuit is to be disabled, PMOStransistor 330 is off because its gate is connected to line 318 which is at logic 11 1, and NMOS tranistor 332 is off because its gate is connected directly to GTL12 ON*. This isolates the drain of PMOS transistor 334 from the high rail 72.13 Transistor 334 is part of a CMOS output driver which drives output line 160 14 and includes NMOS device 336. Likewise, transistor 332 isolates the source of transistor 336 from the low rail 80 so output 160 is placed in tristate mode.16 When GTL ON* is active low and the circuit is to be disabled, PMOS17 transistor 310 is on which couples the high rail (a positive voltage supply 18 exceeding the threshold of the PMOS devices) to the gate of PMOS transistor 19 338 thereby turning it off. Transistor 342 is off when GTL ON* is logic 0. This isolates the drain of the output driver transistor 340 from the high rail thereby 21 disabling it from driving any output signals onto line 344 connected to the 22 gates of the CMOS totem pole output drivers driving line 160. When GTL23 ON* is a logic 1, transistor 310 is off and transistor 342 is on thereby coupling 24 the GTL BIAS control signal on line 149 to the gate of PMOS transistor 338.This causes transistor 338 to act as a load resistor for NMOS driver transistor 1 340 thereby enabling it to convert the analog voltages on line 346 caused by 2 the current steering effect of transistors 300 and 302 under the influence of 3 the input data into output voltages on line 344 compatible with CMOS logic 4 levels. CMOS drivers 334 and 336 then output these voltages on line 160 where there are selectively coupled through programmable FPGA connection 6 devices to one or more FPGA logic blocks.7 Referring to Figure 10, there is shown a circuit diagram for an 8 LVPECLILVDS input circuit that can be used to implement the function of 9 block 154 in Figure 7. The data input from the off-chip LVPECL/LVDS circuit arrives on line 156 only for single ended data. For single ended data, a 11 reference voltage compatible with the LVPECL/LVDS standard is applied to 12 line 159. If the input data is differential in nature, then the complementary 13 signal to the signal on line 156 is applied to line 159.14 NMOS transistors 360 and 362 coupled as a differential pair act as current steering devices to steer the current from a current source 16 implemented by NMOS transistor. Transistors 360 and 362 correspond in 17 function to transistors 88 and 90 in Figure 5. The NBIAS signal on line 165 is 18 coupled to the gate of transistor 364 and controls it to establish the desired 19 level of current flow to give the desired logic level conversion from LVPECULVDS levels to the CMOS levels used inside the FPGA given the 21 load resistances provided by the PMOS load devices 366 and 368.22 Transistors 370 and 372 provide power down enabling and disabling 23 functionality and have their gates coupled to the programming signal 24 LVPECL/LVDS ON* generated by a programming bit during normal operation. When the LVPECL/LVDS ON* signal is active low, PMOS transistor 372 is on. _t _. 1 This shorts the gates of transistors 366 and 368 to their drains and the high 2 rail 110 thereby disabling both load devices and making them essentially 3 infinite impedances. This reduces the current through both NMOS transistors 4 360 and 362 to zero thereby rendering them inoperative. When the LVPECL/LVDS ON* signal is inactive or logic 1, inverter 374 6 drives the gate of PMOS transistor 370 to logic 0 thereby turning it on. When 7 transistor 370 is turned on, the gate and source of transistor are shorted 8 together and the gate of load device 368 is coupled to the gate of transistor 9 366 thereby activating both load devices and transistors 360 and 362. The output signal on line 380 from the current steering activity of 11 transistors 360 and 362 is coupled to the gate of PMOS output driver 12 transistor 376. When the output voltage on line 376 is high, PMOS device 13 376 is off which causes NMOS current source transistor to pull the output 14 voltage on line 388 low. When the voltage on line 380 is high, PMOStransistor 376 is one and will pull line 388 high because power down PMOS16 transistor 378 is on and device 376 overpowers the current source 382.17 PMOS device 376 has its source coupled to NMOS transistor 382 which acts 18 as a current source since its gate is coupled to the NBIAS signal on line 165.19 A deactivated metal mask option transistor 390 provides the ability to adjust the level of current supplied by current source 382. This allows the proper 21 voltage conversion to be made. PMOS transistor 378 acts to disable the 22 output driver 376 by cutting it ofF from the high rail 110 when the 23 LVPECL/LVDS ON* signal is active low. When LVPECL/LVDS ON* is 24 inactive high, PMOS transistor 378 is one and the output driver 376 is operative. 1 The output signal from driver transistor 376 on line 388 is coupled to 2 the gates of totem pole CMOS transistors 384 and 386. These two transistors 3 are disabled by being cut off from the high rail 110 and low rail 96 by PMOS4 transistor 392 and NMOS transistor 394. When the LVPECL/LVDS ON*signal is low, PMOS transistor 392 is off and transistor 394 is off cutting the 6 totem pole drivers off from the high and low rails. This creates a tristate buffer.7 When the LVPECLILVDS ON* signal in inactive, the transistors 392 and 394 8 are turned on and the totem pole drivers are connected to the high and low 9 rails and are active. Referring to Figure 11, there is shown a diagram of a TTLIGTL driver 11 circuit which may be used to implement the function of block 200 in Figure 12 with programmable slew rate. The circuit of Figure 11 basically acts like the 13 circuit of Figure 1 when programmed to be a TTL driver except that the circuit 14 of Figure 12 is used to generate signals on the gate control lines that correspond to lines 30 and 32 in Figure 1. The slew rate is controlled by logic 16 block 400 in response to the state of its input signals CSLEWO and CSLEW 1 17 on bus 202. Likewise, whether the driver functions as a TTL driver like that 18 shown in Figure 1 or a GTL driver like that shown in Figure 2 is also controlled 19 by logic block 400 in accordance with input signal GTL ON* on bus 202. The logic block 400 also controls the tristate output of output line 156 in 21 accordance with the state of the OEN* input on line 208.22 Suppose CSLEWO and CSLEW 1 are set to establish a slow slew rate 23 and GTL ON* is set to establish the driver as a TTL driver. In this case, only 24 transistors 402 and 404 will be activated and transistors 406, 408, 410, and 414 will all be turned off by logic 400 by controlling their gate signals 1 PGATE 2, NGATE 2, PGATE 3, NGATE 3 and NG-GTL to logic states to turn 2 off the transistors the gates of which these signals are driving. In this 3 situation, the DATA IN signal on line 214 causes logic block 400 to drive the 4 PGATE 1 and NGATE 1 signals with the same logic level according to the desired data output. If a logic 0 is to be ouput, both the NGATE 1 and PGATE6 1 signals are driven to logic 1 which turns NMOS transistor 404 on and turns 7 PMOS transistor 402 off. This pulls line 156 low at a slow slew rate. If a logic 8 1 is to be output, the reverse situation is caused by driving both PGATE 1 and 9 NGATE 1 with a logic 0. This turns on 402 and turns off 404 thereby pulling 156 high at a slow slew rate.11 Suppose CSLEWO and CSLEW 1 are set to establish a medium slew 12 rate and GTL ON* is set to establish the driver as a TTL driver. In this case, 13 only transistors 402, 404, 406 and 408 will be activated and transistors 410, 14 412 and 414 will all be turned off by logic 400 by controlling their gate signals PGATE 3, NGATE 3 and NG-GTL to logic states to turn off the transistors the 16 gates of which these signals are driving. In this situation, the DATA IN signal 17 on line 214 causes logic block 400 to drive the PGATE 1, NGATE 1, PGATE 2 18 and NGATE 2 signals with the same logic level according to the desired data 19 output. If a logic 0 is to be ouput, all of the PGATE 1, NGATE 1, PGATE 2 and NGATE 2 signals are driven to logic 1 which turns NMOS transistors 404 21 and 408 on and turns PMOS transistors 402 and 406 off. This pulls line 156 22 low at a medium slew rate. If a logic 1 is to be output, the reverse situation is 23 caused by driving the PGATE 1, NGATE 1, PGATE 2 and NGATE 2 signals 24 with a logic 0. This turns on 402 and 406 and turns off 404 and 408 thereby pulling 156 high at a medium slew rate. 1 Now suppose CSLEWO and CSLEW 1 are set to establish a fast slew 2 rate and GTL ON* is set to establish the driver as a TTL driver. In this case, 3 transistors 402, 404, 406, 408, 410 and 412 will all be activated and transistor 4 414 will be turned off by logic 400 by controlling its gate signal NG-GTL to a logic state to turn off 414. In this situation, the DATA IN signal on line 214 6 causes logic block 400 to drive the PLATE 1, NGATE 1, PLATE 2, NGATE 2, 7 PLATE 3 and NGATE 3 signals with the same logic level according to the 8 desired data output. If a logic 0 is to be ouput, all of the PLATE 1, NGATE 1, 9 PLATE 2, NGATE 2, PLATE 3 and NGATE 3 signals are driven to logic 1 which turns NMOS transistors 404, 408 and 412 on and turns PMOS11 transistors 402, 406 and 410 off. This pulls line 156 low at a fast slew rate. If 12 a logic 1 is to be output, the reverse situation is caused by driving the PLATE13 1, NGATE 1, PLATE 2, NGATE 2, PLATE 3 and NGATE 3 signals with a 14 logic 0. This turns on 402, 406 and 410 and turns off 404 and 408 and 412 thereby pulling 156 high at a fast slew rate.16 If the driver is to be operated as a GTL or GTLP driver, it must emulate 17 the design and function of the circuit in Figure 2 which is a single (open 18 drain0 NMOS device with an external load device. In this situation, logic 19 block 400 controls the PLATE 1, PLATE 2 and PLATE 3 signals so that the PMOS transistors 402, 406 and 410 are always off regardless of the state of 21 the input data on bus 214. NMOS transistors 404, 408, 412 and 414 are then 22 controlled according to the input data and the desired slew rate. For a slow 23 slew rate, only 404 is active and 408, 412 and 414 are all inactive and turned 24 off. For a medium slew rate, 404 and 408 are activated and 412 and 414 are turned off regardless of the state of the input data. A fast slew rate is 1 implemented by activating all of transistors 404, 408, 412 and 414 and driving 2 them according to the input data.3 If output 156 is to be disabled and put in tristate mode, which happens 4 when the OEN* signal is active high, logic block 400 controls the PGATE and NGATE signals and the NG-GTL signal to turn all the PMOS and NMOS6 transistors off regardless of the state of the input data.7 To protect the driver from Vcc levels which are at 5 volts instead of the 8 level for which the transistors are designed for, in the preferred embodiment 9 optional breakdown protection circuits 416 and 418 are used to prevent damage to the operative transistors in case the user connects node 156 to too 11 high of a voltage. In the preferred embodiment, the Vcc protection circuits are 12 extra MOS transistors in series with high and low rail supply lines to each of 13 the PMOS transistors 402, 406 and 410 and NMOS transistors 404, 408, 412 14 and 414. The function of these extra MOS transistors is to be on when the driver is activated so as to impose an IR voltage drop as current flows through 16 the channels of these devices to the sources and drains of the transistors 402, 17 406, 410, 404, 408, 412 and 414. These protection circuits can be omitted in 18 embodiments where the Vcc voltage is guaranteed to never be higher than 19 the design voltage. Referring to Figure 12, there is shown one implementation of logic 21 block 400. The state of the PGATE 1 signal on line 456 is controlled by 22 NAND gate 450. The input to gate 450 are the NOR of OEN* on line 208 and 23 the CGTL ON* signal on line 454. When both OEN* and CGTL ON* are low, 24 NOR gate 452 outputs a logic 1 on line. This causes the PGATE 1 ouput of gate 450 to be controlled by the data on line 214. When OEN* is high 1 indicating the output line 156 is to be tristate or when CGTL ON* is high 2 indicating the device is to be operated as a CGTL and CGTLP driver, line 458 3 is a 0 which causes NAND gate 450 to output a logic 1 for PGATE 1 which 4 turns off PMOS transistor 402 regardless of the state of the data. The PGATE 2 output signal on line 470 has its logic state controlled by 6 NAND gate 472, NOR gate 474 and NAND gate 476 and the input signals 7 CSLEW 1 and CGTL ON* and OEN*. NOR gate 474 outputs a logic 1 when 8 OEN* is low (indicating a desire to enable the output line 156) and the output 9 of NAND gate 476 is low. This happens when CSLEW1 is high indicating a desire for a medium slew rate and CGTL ON* is low indicating a desire for the 11 driver to work as a TTL driver. When gate 474 outputs a logic 1, NAND gate 12 472 drives PGATE 2 in accordance with the data and the driver will be 13 enabled and operating as a TTL driver. When OEN* is high, indicating a 14 desire to tristate output line 156 in Figure 7, NOR gate 474 outputs a logic 0 which forces NAND gate 472 to output a logic 1 regardless of the state of the 16 data input thereby turning off PMOS transistor 406 to help tristate the output 17 line. If CGTL ON* is high, this indicates a desire to activate the CGTL and 18 CGTLP open drain driver architecture like the one shown in Figure 2, and this 19 requires that the upper PMOS transistors in Figure 11 must be turned off. If CGTL ON* is high, inverter 480 outputs a logic 0 which causes NAND gate 21 476 to output a logic 1 and this causes gate 472 to output a logic 1 regardless 22 of the state of the data thereby turning off PMOS transistor 406. The same 23 thing will happen if CGTL ON* is low but CSLEW 1 is low indicating a desire 24 to not have PMOS transistor 406 activated for the medium slew rate. 1 The PGATE 3 output signal on line 482 is controlled by NAND gate 2 483, NOR gate 486 and NAND gate 490 and the input signals CSLEW 0, 3 CGTL ON* and OEN*. NOR gate 486 outputs a logic 1 when OEN* is low 4 (indicating a desire to enable the output line 156) and the output of NANDgate 490 is low. This happens when CSLEWO is high indicating a desire for a 6 fast slew rate and CGTL ON* is low indicating a desire for the driver to work 7 as a TTL driver. When gate 486 outputs a logic 1, NAND gate 483 drives 8 PGATE 3 in accordance with the data and the driver will be enabled and 9 operating as a TTL driver. When OEN* is high, indicating a desire to tristate output line 156 in Figure 7, NOR gate 486 outputs a logic 0 which forces 11 NAND gate 483 to output a logic 1 regardless of the state of the data input 12 thereby turning off PMOS transistor 410 to help tristate the output line. If 13 CGTL ON* is high, this indicates a desire to activate the CGTL and CGTLP14 open drain driver architecture like the one shown in Figure 2, and this requires that the upper PMOS transistors in Figure 11 must be turned off. If CGTL16 ON* is high, inverter 480 outputs a logic 0 which causes NAND gate 490 to 17 output a logic 1 and this causes NAND gate 483 to output a logic 1 regardless 18 of the state of the data thereby turning off PMOS transistor 410. The same 19 thing will happen if CGTL ON* is low but CSLEW 0 is low indicating a desire to not have PMOS transistor 410 activated for the medium slew rate.21 The logic state of the NGATE 1 signal on line 492 in controlled by NOR22 gate 494 and the states of input signals DATA IN on line 214 and the OEN*23 signal on line 208. When OEN* is low indicating a desire for the output line 24 156 in Figures 7 and 11 to be enabled, the logic state of the NGATE 1 signal is controlled solely by the input data. This is because regardless of the slew 1 rate, the NMOS transistor 404 will be active and will only be turned off for 2 tristate mode when OEN* is high.3 The logic state of NGATE 2 signal on line 496 is controlled by NOR4 gate 498 and NAND gate 500 and the logic states of input signals CSLEW 1 and the OEN* signal and the DATA IN signal. When OEN* is high indicating a 6 desire to tristate the output line 156 in Figures 7 and 11, inverter 502 outputs 7 a logic 0 which forces NAND gate 500 to output a logic 1 which forces NOR8 gate 498 to output a logic 0 which turns off NMOS gate 408 to tristate the 9 output because PMOS transistor 406 in Figure 11 of off for the same state of the input signals. When OEN* is low and CSLEW 1 is high, it is an indication 11 that the driver is to be enabled in TTL mode or CGTL or CGTLP mode at a 12 medium slew rate (regardless of whether TTL or CGTL mode is to be used, 13 the NMOS transistors will be used). This state of the inputs causes the output 14 of NOR gate 498 to be controlled by the DATA IN signal on line 214 thereby activating NMOS transistor 408 in Figure 11 and causing it to drive output line 16 156 in accordance with the input data.17 The logic state of NGATE 3 signal on line 502 is controlled by NOR18 gate 504 and NAND gate 506 and the logic states of input signals CSLEW 0 19 and the OEN* signal and the DATA IN signal. When OEN* is high indicating a desire to tristate the output line 156 in Figures 7 and 11, inverter 502 outputs 21 a logic 0 which forces NAND gate 506 to output a logic 1 which forces NOR22 gate 504 to output a logic 0 regardless of the state of the DATA IN signal 23 thereby turning off NMOS gate 412 to tristate the output because PMOS24 transistor 410 in Figure 11 of off for the same state of the input signals. When OEN* is low and CSLEW 0 is high, it is an indication that the driver is to be 1 enabled in TTL mode or CGTL or CGTLP mode at a fast slew rate (regardless 2 of whether TTL or CGTL mode is to be used, the NMOS transistors will be 3 used). This state of the inputs causes the output of NOR gate 504 to be 4 controlled by the DATA IN signal on line 214 thereby activating NMOStransistor 412 in Figure 11 and causing it to drive output line 156 in 6 accordance with the input data.7 The logic state of the NG-GTL signal on line 508 is controlled by the 8 NOR gate 510 and the NAND gate 512 and the input signals DATA IN, OEN*9 and CGTL ON*. When OEN* is high indicating tristate mode is desired, inverter 502 outputs a 0 and NAND gate 512 outputs a logic 1 regardless of 11 the state of the CGTL ON* signal. This forces NOR gate 510 to output a logic 12 0 regardless of the state of the DATA IN signal thereby turning off NMOS13 transistor 414 to tristate output line 156. When OEN* is low, NAND gate 512 14 outputs a signal which depends upon the state of the CGTL ON* signal.When the CGTL ON* signal is high, it indicates the driver is to be activated as 16 a CGTL driver. When the CGTL ON* signal is high and OEN* is low, NAND17 gate 512 outputs a logic 0 which enables NOR gate 510 to drive the gate of 18 NMOS transistor 414 in accordance with the state of the DATA IN signal to 19 drive the output line 156 in Figure 11 thereby emulating the structure and operation of the CGTL and CGTLP driver in Figure 2.21 By a straightforward modification of the logic of Figure 12, it is possible 22 to convert the driver of Figure 11 to an AGTL, HSTL or SSTL driver operating 23 like the driver in Figure 6. To make this modification, it is necessary to re-gate 24 the circuit of Figure 12 so that the PGATE and NGATE signals are selectively turned on with the same logic levels and with the number of PGATE and 1 NGATE signals being simultaneously so driven as to meet the drive 2 requirements for Vol, Voh, currrent sink capability and current source 3 capability. In the claims, the phrase C~TTL or AGTL or HSTL or SSTL format 4 output signalsb means output signals generated at logic levels and with current sink and current source capability to meet a selected one of the TTL6 or AGTL or HSTL or SSTL specifications. As to the input circuits, the phrase 7 Oinput signals having logic 1 and logic 0 voltage levels and reference levels 8 which are characteristics of any of the TTL, GTL, GTLP, LPECL, or LVDS9 circuit familiesb in the claims means input signals having all the characteristics defined in the specifications of a selected one of the TTL, GTL, 11 GTLP, LPECL, or LVDS circuit families.12 Although the invention has been disclosed in terms of the preferred 13 and alternative embodiments disclosed herein, those skilled in the art will 14 appreciate possible alternative embodiments and other modifications to the teachings disclosed herein which do not depart from the spirit and scope of 16 the invention. All such alternative embodiments and other modifications are 17 intended to be included within the scope of the claims appended hereto.

权利要求:
Claims (4)
[1] 1. An apparatus comprising:first means for receiving data at a pin or external connection pad on a field programmable gate array using an input circuit which can be programmed to be compatible with input signals having logic 1 and logic 0 voltage levels and reference levels which are characteristics of a selected one of the TTL, GTL, GTLP, LPECL, or LVDS circuit families and converting said input signals to logic levels which are used in said field programmable gate array, said first means also having inputs for receiving control signals generated from programming bits which control whether said first means functions to convert TTL, GTL, GTLP, LPECL or LVDS format input signals to logic signals at levels compatible with the internal circuitry of said field programmable gate array;second means for receiving data generated within said field programmable gate array at logic levels used in said field programmable gate array and converting the logic levels of this data to output data for driving said pin or external connection pad on a field programmable gate array said output data having logic levels compatible with any of the TTL, GTL or GTLP circuit families, said second means being programmable by means of receiving input signals generated from programming bits said input signals controlling whether said second means functions to convert said logic levels of said data generated in said field programmable gate array to output data having logic levels and current source and sink characteristics compatible with a selected one of the TTL, GTL or GTLP circuit families; and enabling means within said first means and said second means for receiving said control signals generated from said programming bits and controlling said first means so as to define which type of input circuit said first means is to be and controlling said second means to determine which type of driver said second means is to be.
[2] 2. A programmable I/O apparatus for a field programmable gate array comprising:a pin or pad at which are received input signals;a first programmable input circuit having a data input coupled to said pin or pad and to a pair of CMOS transistors, for receiving TTL input signals from said pin or pad and using said pair of series connected CMOStransistors to convert the TTL logic levels of said TTL input signals to logic levels used internally in said field programmable gate array, and having a power down input for receiving a power down programming signal which has a first logic state which causes one or more power down transistors to disable said pair of CMOS transistors and a second logic state which causes said one or more power down transistors to enable said CMOS transistors to operate on said TTL input signals;a second programmable input circuit having a data input coupled to said pin or pad and to a pair of differentially coupled PMOS transistors driving an NMOS output driver transistor which drives a CMOS tristate buffer, for receiving GTL or GTLP input signals from said pin or pad and using said pair of differentially connected PMOS transistors to convert the GTL or GTLP logic levels of said GTL or GTLP input signals to logic levels used internally in said field programmable gate array, and having a bias input for receiving a bias signals which controls the current level output by a current source feeding said differentially coupled PMOS transistors, and having a power down input for receiving a power down programming signal which has a first logic state which causes one or more power down transistors to disable said pair of differentially connected PMOS transistors, disable said NMOS output driver and place said CMOS trisate output buffer in tristate mode and a second logic state which causes said one or more power down transistors to enable said differentially coupled PMOS transistors, enable said NMOS output driver and cause said CMOS tristate output buffer to be enabled to operate on said GTLor GTLP input signals;a third programmable input circuit having a data input coupled to said pin or pad and to a pair of differentially coupled NMOS transistors driving a PMOS output driver transistor which drives a CMOS tristate buffer, for receiving single ended or differential input LVPECL or LVDS signals from said pin or pad and using said pair of differentially connected NMOStransistors to convert the single ended or differential input LVPECL or LVDSsignal logic levels of said input signals to logic levels used internally in said field programmable gate array, and having a bias input for receiving a bias signals which controls the current level output by a current source feeding said differentially coupled NMOS transistors, and having a power down input for receiving a power down programming signal which has a first logic state which causes one or more power down transistors to disable said pair of differentially connected NMOS transistors, and disable said PMOS output driver and place said CMOS trisate output buffer in tristate mode and a second logic state which causes said one or more power down transistors to enable said differentially coupled NMOS transistors, enable said NMOSoutput driver and enable said CMOS tristate output buffer to operate on said GTL or GTLP input signals; and a programmable TTL or GTL/GTLP driver having and output coupled to said pin or pad and have a data input to receive data generated in said field programmable gate array at logic levels used inside said field programmable gate array which are to be driven onto said pin or pad using TTL or GTL or GTL logic levels and drive requirements, said data input coupled to a plurality of pairs of parallel connected CMOS pairs used to generate TTL output signals at programmable slew rates and an NMOS transistor used to generate GTL or GTLP output signals, and hereafter referred to as the operative transistors, said data input coupled to said operative transistors through a network of enable and slew rate control gates which have a power down input for receiving a power down input generated from a programming bit, an input for receiving data generated from programming bits controlling the slew rate and an input for receiving an input signal generated from a programming bit which controls whether said driver is a TTL or GTL/GTLP driver, said enable and slew rate control gates generating from these input signals individual outputs coupled to the gates of said CMOS and NMOS transistors which control whether they function as a TTL driver or a GTL/GTLP driver and which control the slew rate.
[3] 3. An apparatus comprising:first circuit for receiving data at a pin or external connection pad on a field programmable gate array using one or more input circuits comprised of CMOS pairs or differentially coupled NMOS pairs or differentially coupled PMOS pairs which can be selectively enabled and disabled in accordance with the state of control signals generated from programming bits to be compatible with input signals having logic 1 and logic 0 voltage levels and reference levels which are characteristics of a selected one of the TTL, GTL, GTLP, LPECL, or LVDS circuit families, said one or more input circuits functioning to convert said input signals to logic levels which are used in said field programmable gate array, said first circuit also having inputs for receiving control signals generated from programming bits which control which of said input circuits is enabled and disabled so as to control whether said first circuit functions to convert TTL, GTL, GTLP, LPECL or LVDS format input signals to logic signals at levels compatible with the internal circuitry of said field programmable gate array;second circuit for receiving data generated within said field programmable gate array at logic levels used in said field programmable gate array and converting the logic levels of this data to output data for driving said pin or external connection pad on a field programmable gate array, said output data having logic levels compatible with any of the TTL, GTL, GTLP, AGTL, HSTL or SSTL circuit families, said output data being generated using at least one pair of CMOS transistors which may be selectively enabled to generate TTL or AGTL or HSTL or SSTL format output signals at a selectable slew rate and using at least one NMOS transistor which may be selectively enabled to generate GTL or GTLP output signals, said second circuit being programmable by means of receiving control signals generated from programming bits said control signals controlling whether said second circuit functions to convert said logic levels of said data generated in said field programmable gate array to output data having logic levels and current source and sink characteristics compatible with a selected one of the TTL, GTL, GTLP, AGTL, HSTL or SSTL circuit families using a network of enable and slew rate control gates which receive said data generated within said field programmable gate array and said control signals and generates a plurality of individual gate control signals which control the gates of the transistors in said at least one CMOS pair and said at least one NMOS transistor to implement the desired driver type.
[4] 4. An apparatus comprising:first circuit for receiving data at a pin or external connection pad on a field programmable gate array using one or more input circuits comprised of CMOS pairs or differentially coupled NMOS pairs or differentially coupled PMOS pairs which can be selectively enabled and disabled in accordance with the state of control signals generated from programming bits to be compatible with input signals having logic 1 and logic 0 voltage levels and reference levels which are characteristics of a selected one of the TTL, GTL, GTLP, LPECL, or LVDS circuit families, said one or more input circuits functioning to convert said input signals to logic levels which are used in said field programmable gate array, said first circuit also having inputs for receiving control signals generated from programming bits which control which of said input circuits is enabled and disabled so as to control whether said first circuit functions to convert TTL, GTL, GTLP, LPECL or LVDS format input signals to logic signals at levels compatible with the internal circuitry of said field programmable gate array;second circuit for receiving data generated within said field programmable gate array at logic levels used in said field programmable gate array and converting the logic levels of this data to output data for driving said pin or external connection pad on a field programmable gate array, said output data having logic levels compatible with any of the TTL, GTL, GTLP, AGTL, HSTL or SSTL circuit families, said output data being generated using at least one pair of CMOS transistors which may be selectively enabled to generate TTL or AGTL or HSTL or SSTL format output signals or using at least one NMOS transistor which may be selectively enabled in accordance with the state of programming bit to generate GTL or GTLP format output signals.

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公开号 | 公开日 | 专利标题

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同族专利:

公开号 | 公开日

CA2260504A1|2000-05-25|

CA2260504C|2003-08-19|

引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

法律状态:
1999-05-05| EEER| Examination request|

2003-04-29| FZDE| Dead|

优先权:

申请号 | 申请日 | 专利标题

US20019098A| true| 1998-11-25|1998-11-25||

US09/200,190||1998-11-25||

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